Method of making a hybrid substrate having a thin silicon carbide membrane layer

ABSTRACT

A hybrid semiconductor substrate assembly is made by first forming a silicon oxide (SiO x ) layer within a silicon carbide wafer, thus forming a silicon carbide membrane on top of the silicon oxide layer and on a surface of the silicon carbide wafer. Optionally, the silicon oxide layer is then thermally oxidized in the presence of steam or oxygen. A substrate-of-choice is then wafer bonded to the silicon carbide membrane, optionally in the presence of a wetting layer that is located intermediate the substrate-of-choice and the silicone carbide membrane, the wetting layer containing silicon. The silicon oxide layer is then removed by hydrofluoric acid etching, to thereby provide a hybrid semiconductor substrate assembly that includes the substrate-of-choice wafer bonded to the silicon carbide membrane. The hybrid semiconductor substrate assembly is then annealed. The method is repeated a plurality of times, to thereby provide a plurality of hybrid semiconductor substrate assemblies, each assembly including a substrate-of-choice wafer bonded to a silicon carbide membrane. Optionally, an annealing step may be provided after the silicon oxide layer is formed and prior to wafer bonding.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority from pending provisionalpatent application Serial No. 60/272,532 filed Mar. 1, 2001 entitledLARGE AREA HYBRID SiC WAFERS, incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to the field of semiconductor substratemanufacture; i.e., a substrate on which semiconductor materials ordevices can be formed.

[0004] 2. Description of the Related Art

[0005] The present invention makes use of a separation by implantationof oxygen (SIMOX) process.

[0006] In accordance with this invention, a SIMOX process provides thatoxygen implanter apparatus is used to create a very thin silicon dioxide(SiO₂, SiO_(x)) layer that is buried within a relatively thick siliconcarbide (SiC) wafer, thereby leaving a thin membrane layer of SiC on topof the SiC wafer. For example, such oxygen implantation equipment ismanufactured by Ibis Technology Corporation.

[0007] The present invention uses a step of etching SiO₂ (SiO_(x)) inhydrofluoric acid.

[0008] The present invention uses a wafer-bonding step. Wafer bonding ofa variety of materials is known.

[0009] U.S. Pat. No. 5,798,293, incorporated herein by reference, iscited for its teaching of the production of a semiconductor layer of SiCof the 3C polytype on top of a semiconductor substrate layer using awafer-bonding technique.

[0010] U.S. Pat. No. 5,877,070, incorporated herein by reference, iscited for its teaching of transferring an upper portion of a firstmono-crystalline substrate to a second substrate using hydrogentrap-induced implantation of the first substrate, forming micro-cracksin the hydrogen traps, direct wafer bonding the first substrate to thesecond substrate, and growing the micro-cracks such that the upperportion of the first substrate separates from the first substrate.

[0011] U.S. Pat. No. 5,966,620, incorporated herein by reference, iscited for its teaching of the use of the implantation of helium ions orhydrogen ions into a single crystal silicon substrate in order to formmicro-cavities in the implantation region. Separation is achieved due tothe fragility of the implantation region, and by the application of anexternal force, by oxidation of the implantation layer, or by laserheating of the implantation layer.

[0012] U.S. Pat. No. 6,054,370, incorporated herein by reference, iscited for its teaching of the formation of first damaged regions in asubstrate underneath areas wherein active devices are formed formingsecond damaged areas in the substrate at locations between the firstdamaged regions, causing a film to detach from the substrate atlocations where the first and second damaged regions are formed, andtransferring the film to a wafer.

[0013] U.S. Pat. No. 6,120,597, incorporated herein by reference, iscited for its teaching of the detaching of a single crystal film from anepilayer/substrate or bulk crystal structure wherein ions are implantedinto the crystal structure to form a damaged layer within the crystalstructure at an implantation depth below a top surface of the crystalstructure, and wherein chemical etching effects detachment of the singlecrystal film from the crystal structure.

SUMMARY OF THE INVENTION

[0014] This invention provides for the fabrication of hybrid substrateswherein a thin membrane of SiC is lifted off or sliced from a relativelythick SiC wafer, and wherein the thin SiC membrane is wafer bonded tothe surface of a substrate-of-choice, to thereby form a hybrid substratethat is made up of the thin membrane of SiC and the substrate-of-choice.

[0015] While the invention will be described relative to the use of arelatively thick SiC wafer within the spirit and scope of the inventionsuch a semiconductor wafer can be selected from SiC polytypes,non-limiting examples being 6H-SiC, 4H-SiC, 3C-SiC and 15R-SiC.

[0016] Use of the relatively thick and expensive SiC wafer is maximizedsince many thin SiC membranes can be produced from one thick SiC wafer.That is, the thick and expensive SiC wafer can be re-used to form anumber of thin SiC membranes wherein the now-exposed surface of therelatively thick SiC wafer is polished before the next thin SiC membraneis removed from the thick SiC wafer.

[0017] Wafer bonding of the SiC membrane to the substrate-of-choice isperformed using commercially-available substrates-of-choice. In thismanner, the invention provides relatively inexpensive hybrid SiCsubstrates.

[0018] An embodiment of the invention includes a three-step process. Inthis three-step process, a buried SiO₂ layer, or more generally aSiO_(x) layer, is first formed in a relatively thick SiC wafer by oxygenimplantation at an elevated temperature thereby forming a thin SiCmembrane on top of the buried SiO₂ layer.

[0019] Secondly, the exposed surface of the thin SiC membrane is waferbonded to the surface of a substrate-of-choice; for example, to asilicon (Si), or a polycrystalline SiC substrate. Optionally, awetting/bonding layer can be provided between the two wafer-bondingsurfaces. Non-limiting examples of such a wetting/bonding layer arelayers that contain silicon, such as silicon nitride (Si₃N₄).

[0020] Thirdly, the thin SiC membrane is separated from the relativelythick SiC wafer; for example, by using a hydrofluoric acid etching stepto remove the buried SiO₂ (SiO_(x)) layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIGS. 1A, 1B and 1C show a three-step process by which hybridsubstrates having a thin SiC membrane are produced in accordance withthe invention, wherein

[0022]FIG. 1A shows a buried SiO₂ (SiO_(x)) layer that is formed withina SiC wafer by oxygen implantation, thereby leaving a top disposed andthin SiC membrane,

[0023]FIG. 1B shows a substrate-of-choice that has been wafer bonded tothe top and exposed surface of the thin SiC membrane, and

[0024]FIG. 1C shows that the thin SiC membrane has been lifted off,removed from, sliced from, or separated from, the top of the SiC waferby etching SiC wafer 11 in hydrofluoric acid, the result being a thinSiC membrane that is wafer bonded onto the substrate-of-choice.

[0025]FIG. 2A shows how a number of thin and circular SiC membranes arewafer bonded onto the surface of a circular substrate of choice.

[0026]FIG. 2B shows how a number of thin and hexagonally-shaped SiCmembranes are wafer bonded onto the surface of a circularsubstrate-of-choice.

[0027]FIG. 2C shows how a number of thin and four-sided SiC membranesare wafer bonded onto the surface of a circular substrate-of-choice.

[0028]FIGS. 3A and 3B show a method in accordance with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0029] With reference to FIG. 1A in accordance with the invention aburied SiO₂ or SiO_(x) layer 10 (hereinafter SiO₂) is formed in a SiCwafer 11 by oxygen implantation, thereby leaving a top disposed and thinSiC membrane 12 that is, for example, about one micrometer thick orless. The oxygen implantation step of FIG. 1A is usually performed at ahigh temperature; for example, from about 600 to about 700 degreescentigrade.

[0030] As a feature of the invention, a thermal oxidation step may beprovided, for example at a temperature about 1150 degrees centigrade andin steam (wet oxidation) or in dry oxygen (dry oxidation), in order togrow SiO₂ layer 10, thereby redistributing and smoothening the bondinterface that exists between SiO₂ layer 10 and SiC membrane 12.

[0031] In FIG. 1B, a substrate-of-choice 13, for example a silicon (Si)substrate 13, is wafer bonded to the top, polished, and exposed surface14 of thin SiC membrane 12. FIG. 1B shows an optional Si₃N₄ wettinglayer 15 that can be provided between the top surface 14 of thin SiCmembrane 12 and the bottom surface 20 of substrate-of-choice 13 prior towafer bonding.

[0032] As used herein, the term wafer bonding is intended to mean amethod of securely bonding two materials together that may haveincompatible growth and processing technologies, wherein two polishedand flat surfaces of almost any material are brought into physicalcontact so as to be locally attracted to each other by van der Waalsforces, thus resulting in the bonding of the two polished and flatsurfaces. In practice, wafer-bonding processes often requires anelevated temperature, a controlled atmosphere, and an elaborate surfacecleaning procedure. Usually, the wafer-bonding process is performed in aclean environment to avoid particle contamination between the two flatbonding surfaces since contamination can cause unbonded surface areas tooccur. After physically contacting the two polished and flat surfaces,bonding usually begins in one surface location, typically after applyinga slight pressure. The bonded surface area then spreads laterally overthe area of the two contacting surfaces within a few seconds, generallyindependent of wafer thickness and distance from the rim of the wafer.Compression and liquid surface tension helps the two surfaces conform toeach other, thus assuring good contact even when the individualcontacting surfaces are slightly non-parallel. Crystallites within thetwo contacting surface can fuse together at elevated temperatures due tosurface energy induced migration, or due to the formation of bondsbetween the surface species (i.e., Si—C or Si—Si, when bonding SiC toSi). In a nonlimiting embodiment of the invention wafer-bonding wasperformed at a temperature of from about 500 to about 1000 degrees, inthe presence an uniaxial pressure, and in the presence of a forming gassuch as a mixture of hydrogen and nitrogen.

[0033] In the process step of FIG. 1B, the intermediate wetting/bondinglayer 15 that contains silicon (Si₃N₄) may be provided, if desired, toimprove the strength of the wafer bonding of substrate-of-choice 13 toSiC membrane 12.

[0034] In the process step of FIG. 1C, the thin SiC membrane 12 has beenlifted off, or separated from, the top of FIG. 1A SiC wafer 11 byetching SiO₂ layer 10 in hydrofluoric acid. The result is a thin SiCmembrane 12 that is wafer bonded onto the surface 20 ofsubstrate-of-choice 13. As a feature of the invention, a hightemperature annealing step may be provided for the substrate assembly12,13.

[0035] A final Chemical Mechanical Polishing (CMP) step may now beperformed on the now-exposed top surface 21 of relatively thick wafer22.

[0036] Substrate-of-choice 13 is selected in accordance with an end userapplication in order to optimize the electrical properties, the thermalconductivities, and/or the insulating properties of substrate-of-choice13 in accordance with the application. Applications where this inventionfinds utility include large-area substrates-of-choice 13 for use in RFapplications (insulating substrates), near DC power and optical devices(conducting substrates), and for use as seeds for large-diameter boulegrowth. As will be appreciated, the choices for substrate-of-choice 13can vary widely for different applications.

[0037] Substrate-of-choice 13 for SiC epitaxial growth requiresmechanical stability and the ability to withstand temperatures as highas 1700° C. The use of polycrystalline SiC, sapphire, polycrystalline orcrystalline AlN for applications requiring semi-insulating properties,and diamond and polycrystalline SiC for applications requiringconducting properties, are suggested for substrate-of-choice 13.

[0038] Substrate-of-choice 13 selections for III-V nitride growthrequire mechanical stability and the ability to withstand temperaturesas high as 1100° C. The use of polycrystalline SiC, silicon oxide andsilicon nitride for applications requiring semi-insulating properties,and silicon for applications requiring conducting properties, aresuggested for substrate-of-choice 13.

[0039] Substrate-of-choice 13 selections for use in seeding SiC boulegrowth include crystalline SiC membranes bonded to polycrystalline SiC.

[0040] Substrate-of-choice 13 selections for thermal considerationsinclude polycrystalline SiC and diamond.

[0041] There are several ways to scale the diameter 25 ofsubstrate-of-choice 13 by wafer bonding a number of thin SiC membranes12 to each substrate-of-choice 13, as is illustrated by FIGS. 2A, 2B and2C, wherein SiC membranes 12 are of a circular shape in FIG. 2A, SiCmembranes 12 are of a hexagonal shape in FIG. 2B, and SiC membranes 12are a square shape in FIG. 2C. In these figures, the diameter 20 ofsubstrate-of-choice 13 is, for example, about 6 inches.

[0042] The present invention provides for the making of large area SiCmembranes 12 that also have utility as seeds for use in boule growth. Inthis utility, SiC membranes 12 can be provided that are as much as 3times larger diameter than is available using known SiC boule seedtechnology. In this utility, it is desirable that membranes 12 beprovided that are thicker than the above-mentioned example of about onemicrometer thick or less.

[0043] With reference to FIG. 1A, and in accordance with an embodimentof the invention, a 4H-SiC wafer 11 was first ion-implanted with oxygenat 1.5 MeV and 700° C., thus providing a buried SiO_(x) layer 10 thatwas about 1 μm below the top surface 14 of the 4H-SiC wafer 11. The SiCmembrane maintained good crystalline quality as was determined by theuse of a Rutherford Backscattering Spectroscopy.

[0044] Second, a highly-reproducible wafer-bonding process provideddirect wafer bonding of the top surface 14 of the 4H-SiC membrane 12 toeither a conducting (Si) or an insulating (SiO₂) substrate-of-choice 13.A strong bond and a good electrical interface was observed at thewafer-bonded interface 30 between 4H-SiC membrane 12 andsubstrate-of-choice 13.

[0045] Third, an efficient acid etch lift-off process provided that thin4H-SiC membrane 12 was separated from the remainder 22 of the 4H-SiCwafer 11, as the separated 4H-SiC membrane 12 remained bonded to the Sior SiO₂ substrate-of-choice 13. Good reproducibility and high yield wereobtained.

[0046] Size scaling of the above process was demonstrated using 3C-SiCto form wafer 11 to thereby provide sizes of membrane 12 up to about 2×2cm.

[0047]FIGS. 3A and 3B show a method in accordance with the inventionwherein in step 30 SiC wafer 11 is provided, and in step 31 SiC wafer 11is subjected to an oxygen-implantation step to thereby form a surfacelocated SiC membrane 12 that is located on top of a buried SiO₂ layer10.

[0048] Step 32 is an optional thermal-oxidation step that may beprovided to smoothen the interface between buried SiO₂ layer 10 and SiCmembrane 12.

[0049] Step 33 provides an optional step whereby wafer 11 and its buriedSiO₂ layer 10 are high-temperature annealed.

[0050] Step 34 provides a substrate of choice 13, whereas step 35optionally provides a wetting layer 15 that contains Si and is locatedintermediate substrate-of-choice 13 and SiC membrane 12.

[0051] Wafers 11 and substrates of choice 13 of the type that are usedin accordance with this invention usually include visual indicators, forexample flats or cuts, that indicate the alignment direction of thecrystals that form members 13 and 11. As a feature of the invention, anoptional step 36 may be provided to physically align SiC membrane 12 andsubstrate-of-choice 13 prior to the above-described wafer-bonding stepso as to optimize the bonding of the two crystal interfaces that areprovided by the two surfaces that are to be wafer bonded.

[0052] In step 37, substrate-of-choice 13 is wafer bonded to SiCmembrane 12, and in step 38, the SiO₂ layer 10 of FIG. 1B is removedusing a hydrofluoric acid bath.

[0053] In optional step 39, the FIG. 1C substrate assembly is annealedat a high temperature.

[0054] Relative to annealing step-33 and annealing step-39, it may bethat the use of only one such step is sufficient. The utility of such ahigh temperature annealing step, or steps, is to repair any ionimplantation induced damage that may be present within SiC membrane 12.

[0055] In step 40, the method of FIGS. 3A and 3B is repeated a number oftimes in order to maximize the use of the thickness of SiC wafer 11, andin order to produce a plurality of the FIG. 1C hybrid substrates, eachhybrid substrate including a substrate-of-choice 13 that is wafer bondedto a SiC membrane 12.

[0056] The invention has been described in detail while making referenceto preferred embodiments thereof. However, this detailed description isnot to be taken as a limitation on the spirit and scope of theinvention.

What is claimed is:
 1. The method of making a hybrid substrate assemblycomprising the steps of: providing a semiconductor wafer having a firstcomposition; implanting an oxide layer within said semiconductor waferto thereby form a semiconductor membrane on a surface of saidsemiconductor wafer; providing a substrate-of-choice having a secondcomposition that is different than said first composition; wafer bondingsaid substrate-of-choice to said semiconductor membrane; and removingsaid oxide layer to thereby provide a hybrid substrate assembly thatincludes said substrate-of-choice wafer bonded to said semiconductormembrane.
 2. The method of claim 1 including the step of: aligning acrystalline construction of said substrate-of-choice to a crystallineconstruction of said semiconductor membrane prior to said wafer bondingstep.
 3. The method of claim 1 including the step of: providing awetting layer intermediate said substrate-of-choice and saidsemiconductor membrane, said wetting layer having an element that iscommon to said first composition and said second composition.
 4. Themethod of claim 1 including the step of: thermally oxidizing said oxidelayer prior to said wafer-bonding step.
 5. The method of claim 1 whereinsaid step of implanting said oxide layer within said semiconductor waferand said step of removing said oxide layer respectively comprise anoxygen-implantation step and an acid-etching step.
 6. The method ofclaim 4 including the step of: providing a wetting layer intermediatesaid substrate-of-choice and said semiconductor membrane prior toperforming said wafer-bonding step.
 7. The method of claim 1 includingthe step of: subjecting said hybrid substrate assembly to an annealingstep.
 8. The method of claim 7 including the step of: thermallyoxidizing said oxide layer prior to said removing step.
 9. The method ofclaim 8 wherein said step of implanting said oxide layer within saidsemiconductor wafer and said step of removing said oxide layerrespectively comprise an oxygen-implantation step and an acid-etchingstep.
 10. The method of claim 9 including the step of: providing awetting layer intermediate said substrate-of-choice and saidsemiconductor membrane prior to performing said wafer-bonding step. 11.The method of claim 1 including the step of: repeating said implantingstep, said wafer bonding step, and said removing step a plurality oftimes relative to a plurality of substrates-of-choice, to therebyprovide a plurality of hybrid substrate assemblies that each include asubstrate-of-choice wafer bonded to a semiconductor membrane.
 12. Themethod of making a hybrid substrate assembly comprising the steps of:providing a wafer selected from SiC polytypes such as 6H-SiC, 4HSiC,3C-SiC and 15R-SiC; forming a SiO_(x) layer within said wafer to therebyform a wafer membrane on a surface of said wafer; providing asubstrate-of-choice; wafer bonding said substrate-of-choice to saidwafer membrane; and removing said SiO_(x) layer to thereby provide ahybrid substrate assembly that includes said substrate-of-choice waferbonded to said wafer membrane.
 13. The method of claim 12 including thestep of: thermally oxidizing said SiO_(x) layer prior to said removingstep.
 14. The method of claim 12 including the step of: providing awetting layer intermediate said substrate-of-choice and said wafermembrane prior to said wafer-bonding step.
 15. The method of claim 14wherein said wetting layer contains silicon.
 16. The method of claim 15wherein said wetting layer is a layer that contains silicon, such asSi₃N₄.
 17. The method of claim 12 including the step of: annealing saidwafer after said forming step.
 18. The method of claim 12 including thestep of: annealing said hybrid substrate assembly.
 19. The method ofclaim 12 wherein said substrate-of-choice is selected from a groupincluding Si, SiO₂, polycrystalline SiC, sapphire, polycrystalline AlN,crystalline AlN, diamond and Si₃N₄.
 20. The method of claim 12 whereinsaid wafer is SiC.
 21. The method of claim 12 wherein said removing stepcomprises etching said SiO_(x) layer in hydrofluoric acid.
 22. Themethod of claim 12 wherein said step of forming said SiO_(x) layerwithin said wafer and said step of removing said SiO_(x) layer,respectively, comprise an oxygen-implantation step and an acid-etchingstep.
 23. The method of claim 12 including the step of: repeating saidforming step, said wafer bonding step, and said removing step aplurality of times relative to a plurality of substrates-of-choice tothereby provide a plurality of hybrid substrate assemblies that eachinclude a substrate-of-choice wafer bonded to a wafer membrane.
 24. Themethod of claim 12 wherein SiO_(x) is SiO₂.
 25. The method of claim 24wherein said wafer membrane is one micrometer thick or less.
 26. Themethod of claim 12 including the step of: optimizing said wafer-bondingstep by aligning a crystalline nature of said wafer and saidsubstrate-of-choice prior to said wafer-bonding step.
 27. The method ofmaking a hybrid substrate assembly comprising the steps of: providing aSiC wafer; forming a SiO_(x) layer within said SiC wafer to thereby forma SiC membrane on a surface of said SiC wafer; thermally oxidizing saidSiO_(x) layer; providing a substrate-of-choice; providing a wettinglayer that contains Si intermediate said substrate-of-choice and saidSiC membrane; wafer bonding said substrate-of-choice to said SiCmembrane; and removing said SiO_(x) layer to thereby provide a hybridsubstrate assembly that includes said substrate-of-choice wafer bondedto said SiC membrane.
 28. The method of claim 27 wherein said thermaloxidation step takes place in the presence of steam or oxygen.
 29. Themethod of claim 27 wherein said wetting layer is Si₃N₄.
 30. The methodof claim 27 including the step of: annealing said SiC wafer after saidforming step.
 31. The method of claim 27 including the step of:annealing said hybrid substrate assembly.
 32. The method of claim 27wherein said substrate of choice is selected from a group including Si,SiO₂, polycrystalline SiC, sapphire, polycrystalline AlN, crystallineAlN, diamond and Si₃N₄.
 33. The method of claim 27 wherein said wafer isselected from SiC polytypes.
 34. The method of claim 27 wherein saidremoving step comprises etching said SiO_(x) layer in hydrofluoric acid.35. The method of claim 27 wherein said step of forming said SiO_(x)layer within said SiC wafer and said step of removing said SiO_(x) layerrespectively comprise an oxygen-implantation step and an acid-etchingstep.
 36. The method of claim 27 including the step of: repeating saidforming step, said thermal oxidizing step, said providing a wettinglayer step, said wafer-bonding step, and said removing step a pluralityof times relative to a plurality of substrates-of-choice to therebyprovide a plurality of hybrid substrate assemblies that each include asubstrate-of-choice wafer bonded to a SiC membrane.
 37. The method ofclaim 27 wherein said SiO membrane is about one micro meter thick. 38.The method of claim 27 including the steps of: determining a crystallinestructure of said SiC wafer and a crystalline structure of saidsubstrate-of-choice; and physically aligning said crystalline structureof said SiC membrane to said crystalline structure of said SiC waferprior to said wafer-bonding step.
 39. The method of making a hybridsubstrate assembly comprising the steps of: providing a wafer selectedfrom SiC polytypes such as 6H-SiC, 4HSiC, 3C-SiC, and 15R-SiC; forming aSiO_(x) layer within said wafer by means of oxygen implantation, tothereby form a wafer membrane on a surface of said wafer; thermallyoxidizing said SiO_(x) layer; providing a substrate-of-choice; providinga wetting layer that contains Si intermediate said substrate-of-choiceand said wafer membrane; wafer bonding said substrate-of-choice to saidwafer membrane; and removing said SiO_(x) layer to thereby provide ahybrid substrate assembly that includes said substrate-of-choice waferbonded to said wafer membrane.
 40. The method of claim 39 wherein saidthermal oxidation step takes place in the presence of steam or oxygen.41. The method of claim 39 including the step of: annealing said waferafter said forming step.
 42. The method of claim 39 including the stepof: annealing said hybrid substrate assembly.
 43. The method of claim 39wherein said substrate of choice is selected from a group including Si,SiO₂, polycrystalline SiC, sapphire, polycrystalline AlN, crystallineAlN, diamond and Si₃N₄.
 44. The method of claim 39 including the stepof: repeating said forming step, said thermal oxidation step providing awetting layer step, said wafer bonding step, and said removing step aplurality of times relative to said wafer and relative to a plurality ofsubstrates-of-choice, to thereby provide a plurality of hybrid substrateassemblies that each include a substrate-of-choice wafer bonded to awafer membrane.
 45. The method of claim 39 wherein said wafer membraneis no greater that about one micro meter thick.
 46. The method of claim39 including the steps of: determining a first crystalline structure ofsaid wafer; determining a second crystalline structure of saidsubstrate-of-choice; determining an alignment of said first crystallinestructure to said second crystalline structure that will enhance waferbonding of said wafer membrane to said substrate-of-choice; and aligningsaid wafer membrane with respect to said substrate-of-choice inaccordance with said determined alignment prior to said wafer-bondingstep.